1. Field of the Invention
The present invention relates to a circuit for aligning data transmission and a related method, and more particularly, to a circuit for aligning data transmission timing of a plurality of lanes and a related method.
2. Description of the Prior Art
Recently, computer systems usually adopt a peer-to-peer link (such as, a peer-to-peer link defined by Peripheral Component Interconnect Express (PCI-Express)) as a two-way communication between other peripheral devices. As one skilled in the art well-known, the PCI-Express bus can use a higher operational clock and additional lanes in order to improve its data transfer performance. Please refer to FIG. 1, which is a diagram of a conventional PCI-Express bus 115 utilizing a plurality of lanes to transmit data. Suppose that a data stream 110 is transmitted from a transmitting device 100 to a receiving device 120. Since the PCI-express bus 115 can provide four lanes including LANE0, LANE1, LANE2, and LANE3, these bytes D0-D7 included in the data stream 110 together with a corresponding COM symbol are respectively transmitted via the lanes LANE0, LANE1, LANE2, and LANE3 when the transmitting device 100 outputs the data stream 110. In other words, a COM symbol together with two bytes D0 and D4 are passed to the receiving device 120 through the lanes LANE0, a COM symbol together with two bytes D1 and D5 are passed to the receiving device 120 through the lane LANE1, a COM symbol together with two bytes D2 and D6 are passed to the receiving device 120 through the lane LANE2, and a COM symbol together with two bytes D3 and D7 are passed to the receiving device 120 through the lane LANE3. In the end, the receiving device 120 is capable of acquiring the desired data stream 110 via the four lanes LANE0, LANE1, LANE2, and LANE 3.
Generally speaking, the transmitting device 100 respectively outputs ordered sets to lanes LANE0, LANE1, LANE2, and LANE3 at the same time. However, the lanes LANE0, LANE1, LANE2, and LANE3 might have different lengths and impedance owing to different circuit layouts. That is, during the data transmission, the lanes LANE0, LANE1, LANE2, and LANE3 might introduce different delays. Therefore, there is a skew existed between the data transmission timing of the lanes LANE0, LANE1, LANE2, and LANE3. In other words, even if the transmitting device 100 synchronously outputs the COM symbol to lanes LANE0, LANE1, LANE2, and LANE3, the COM symbols of lanes LANE0, LANE1, LANE2, and LANE3 are unable to arrive to the receiving device 120 at the same time. Therefore, because the transmission timing of the lanes LANE0, LANE1, LANE2, and LANE3 has skews, the receiving device 120 is unable to process bytes D0, D1, D2, and D3 transmitted via the lanes LANE0, LANE1, LANE2, and LANE3 at the same time.
Please refer to FIG. 2, which is a diagram of another conventional PCI-Express bus 215 utilizing a plurality of lanes to transmit data. In this embodiment, the operating clock applied to the transmitting device 200 is different from that of the receiving device 220. If the operating clock of the transmitting device 200 has a frequency greater than the frequency of the operating clock applied to the receiving device 220, the data transmitting rate of the data stream 210 outputted from the transmitting device 200 will be greater than the data receiving rate of the data stream 210 received by the receiving device 220, accordingly. Therefore, it may result in a data overflow. On the contrary, if the operating clock of the transmitting device 200 has a frequency less than a frequency of the operating clock applied to the receiving device 220, the data transmitting rate of the data stream 210 outputted from the transmitting device 200 will be less than the data receiving rate of the data stream received by the receiving device 220, accordingly. Therefore, it may result in a data underflow.
In order to solve the problems generated from a mismatch of the operating clocks on the transmitting device 200 and the receiving device 220, the receiving device 220 has a plurality of elastic buffers to regulate data outputted from the transmitting device 200 and transferred through lanes LANE0, LANE1, LANE2, and LANE3. Based on the specification of the PCI-Express bus, the transmitting device 200 outputs ordered sets to make the elastic buffers balance different operating clocks adopted by the transmitting device 200 and the receiving device 220. For example, each ordered set outputted from the transmitting device 200 includes a COM symbol and three SKP symbols. When an elastic buffer located on the receiving device 220 receives a plurality of ordered sets, the elastic buffer reduces the number of SKP symbols in these ordered sets if the operating clock of the transmitting device 200 has a frequency greater than that of the operating clock applied to the receiving device 220. As a result, the data transmitting rate of the transmitting device 200 is accordingly reduced, and the above data overflow problem can be avoided. However, the elastic buffer increases the number of SKP symbols in these ordered sets if the operating clock of the transmitting device 200 has a frequency less than that of the operating clock applied to the receiving device 220. Therefore, the data transmitting rate of the transmitting device 200 is accordingly boosted, and the above data underflow problem can be avoided.
However, this approach may result in inconsistency on the number of SKP symbols for each lane, such that there maybe an offset occurred in the data transmission timing of the lanes LANE0, LANE1, LANE2, and LANE3. For example, as shown in FIG. 2, the elastic buffers EB0, EB1, EB2, and EB3 are used to adjust (increase or decrease) the number of SKP symbols in ordered sets, respectively. After adjustment, the ordered sets of the lane LANE0 have one COM symbol as well as three SKP symbols, the ordered sets of the lane LANE1 have one COM symbol as well as four SKP symbols, the ordered sets of the lane LANE2 have one COM symbol as well as three SKP symbols, and the ordered sets of the lane LANE3 have one COM symbol as well as two SKP symbols. Obviously, there is an offset occurred in the data transmission timing of the lanes LANE0, LANE1, LANE2, and LANE3. In other words, the receiving device 220 is unable to process the bytes D0, D1, D2, and D3 transferred on the lanes LANE0, LANE1, LANE2, and LANE3 at the same time.
Hence, how to calibrate the data transmission timing of a plurality of lanes has become an important topic in the field of PCI-Express bus, such that the receiving device is able to extract the desired data stream correctly.